2017.B.4.4. ARM Triple Core Lock Step Architecture for Space


Balaji Venu (1)
Emre Ozer (1)
Xabier Iturbe (1)
Toby Proctor (1)

  1. ARM Ltd, United Kingdom




soft error, fail functional, resiliency


This talk will introduce ARM Triple Core Lock Step (TCLS) architecture, which builds upon the success of ARM Cortex-R5 Dual Core Lock Step (DCLS) processor, currently used in safety critical real time applications. TCLS features fail functional capability, implementing three Cortex-R5 CPUs in lock-step mode making it completely resilient to soft errors from a CPU perspective.

The main radiation effects on electronic components in space are Total Ionizing Diode (TID), Total Non-Ionizing Doze (TNID) and Single event effects (SEE). Rad Hard technology primarily addresses TID radiation effects on Silicon technology. However, they are still vulnerable to SEEs caused by heavy ion bombardment. For missions, which will require high levels of soft error resiliency, TCLS architecture offers complete soft error resiliency from a CPU point of view. TCLS architecture will be an excellent addition to the existing Rad Hard Technology and other fault tolerance techniques like ECC used by the space community.

TCLS architecture implements three Cortex-R5 CPUs in lock-step mode, a majority voter and error detection and correction logic to resynchronize the CPUs when they diverge due to a soft error. The resynchronization process is transparent to software and only takes a few micro-seconds to complete (2,500 clock cycles), thereby reducing the system downtime by an approximate 1000x factor compared with Cortex-R5 DCLS. TCLS can still work safely with two functionally correct CPUs, the system can be configured to execute the resynchronization routines only when it is not performing any critical operations, thus meeting hard real-time deadlines.

As the TCLS architecture provides reliability at the system level, individual CPUs do not need to be fault-tolerant, and can be implemented using commercial process technology that provides higher performance, better energy and cost efficiency than rad-hard process technology. TCLS logic was designed and implemented using commercial technology and compared against single core rad hard technology. The Power Performance Area results of TCLS IP are comparable to the Cortex-R5 single-core implementation but unlike in single-core, TCLS provides the means to detect and recover from virtually all SEUs that affect the processor.

TCLS-based SoC will be made available to academia for education and research purposes through ARM university program team, as a reference SoC design on a FPGA with an OS ported and example applications. We are also willing to collaborate with universities, space agencies and industry to use the TCLS IP to build CubeSats, On Board Computers or to control payload avionics.


  • Will be made available for download after the workshop

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